Recently, in order to address the issue of microtechnology in the field of nonvolatile memory devices, extensive research is being conducted to improve the integration density of these memory devices by stacking memory cells in a three-dimensional structure. In particular, active research is being conducted on the stacking of memory cells in the field of new memory devices, such as Phase-change Random Access Memory (PRAM) and Resistive Random Access Memory (RRAM).
In a typical memory cell array, a plurality of word lines and a plurality of bit lines intersect perpendicularly to each other, and memory cells are disposed at the intersections between the word lines and the bit lines. The memory cell at the intersection between the word line and the bit line is selected by an address, and data is read from the selected memory cell through the bit line. Each memory cell has a selector for the memory cell selection.
Examples of the selectors for selection of the stacked memory cells include planar-type metal oxide semiconductor field effect transistors (MOSFETs), macaroni-type MOSFETs, and diodes. The planar-type MOSFETs are not suitable for planar micronization and cannot increase the planar integration density. The macaroni-type MOSFETs are suitable for planar micronization, but typically require a complex fabrication process. Because the diodes have a simple structure, they are suitable for micronization and do not require a complex fabrication. Thus, the diodes are most useful as selectors of stacked memory cells.
FIG. 16 is a circuit diagram illustrating an equivalent circuit of a memory cell array that uses diodes as selectors of stacked memory cells. For the convenience of description, FIG. 16 illustrates only three-layered stacked memory cells MC1, MC2, MC3 and MC12 and bit lines BL1 and BL3 and word lines WL2, WL4 and WL22 connected to the memory cells, while omitting the illustration of other memory cells arranged in the directions of word lines and bit lines.
Each memory cell includes a diode (as a selector) and a resistor with a resistance value corresponding to memory data. The resistor and the memory are connected in series between the word line and the bit line. The diode is connected in the forward bias direction when the bit line has a higher potential than the word line. Furthermore, the word line and the bit line are alternately stacked to be shared by two layers of memory cells that are adjacent to each other.
For example, if data is being read from the second-layer memory cell MC2, the word line WL2 is selectively driven at a low level 0V by a decoder circuit (not illustrated) and the bit line BL3 is selectively biased at a predetermined high level Vsel. In this bias state, a current value is detected by a sense amp (not illustrated) connected to the bit line BL3 and the logic value (0 or 1) of the memory data of the memory cell MC2 is determined from the detection result prior to output to an external device.
If the word line and the bit line are shared between the adjacent layers and a diode is used as a selector of the stacked memory cells, the word line WL2 is selectively driven at the low level and the bit line BL3 is selectively biased at the high level to cause the diode of the memory cell MC2 (i.e., the read target) to be forward biased. On the other hand, if the word line WL2 is driven at the high level and the bit line BL3 is biased at the low level, the diode of the memory cell MC2 is reverse biased. Regardless, if the resistance value of the resistor of the memory cell MC2, a current does not flow from the memory cell MC2 to the bit line BL3. In other words, the memory cell MC2 is unselected and a memory data read operation is not performed.
However, the diode is a 2-terminal device and its conduction state is determined by the voltage relationship between its anode and cathode. Therefore, as described above, if the word line and the bit line are shared between the adjacent layers and the diode is used as the selector of the stacked memory cells, a current may be generated between the word line or bit line of the selected layer and the word line or bit line of the unselected layer according to the voltage states of the bit line and the word line connected to the memory cell of the unselected layer. Thus, power consumption may increase and a normal read operation may be hindered as discussed below with respect to FIG. 16
In the above-described example, in order to read data from the memory cell MC2 of the second layer (i.e., the selected layer), the word line WL2 is driven at the low level 0V and the bit line BL3 is biased at the high level Vsel. If the word line WL4 connected to the memory cell MC3 of the third layer (i.e., the unselected layer) is floated, a charge current IL1 of a parasitic capacitance (not illustrated) of the word line WL4 flows from the bit line BL3 through the memory cell MC3 to the word line WL4. Consequently, the sense amp (not illustrated) connected to the bit line BL3 detects the charge current IL1 flowing through the memory cell MC3 of the unselected layer, in addition to the current flowing through the memory cell MC2 of the selected layer. Thus, a current of the memory cell MC2 of the selected layer cannot be normally detected and a read operation is hindered. Also, power consumption increases because a charge current IL1 of the parasitic capacitance of the word line WL4 is generated.
Furthermore, if the bit line BL1 connected to the memory cell MC1 of the first layer (i.e., the unselected layer) is floated, a leakage current IL2 of another memory cell MC12 of the same layer as the memory cell MC1 flows through the bit line BL1 and the memory cell MC1 to the word line WL2. In particular, not only the selected memory cell MC1, but also the unselected memory cell MC12, are connected to the bit line BL1. The word line WL22 connected to the memory cell MC12 is driven at the high level Vsel. On the current path between the word line WL22 driven at the high level Vsel and the word line WL2 driven at the low level 0V, the diode of the memory cell MC12 is reverse biased and the reverse leakage current IL2 flows through the bit line BL1 and the memory cell MC1 to the word line WL2.
There are a plurality of memory cells on the bit line BL1 that have the same bias state as the memory cell MC12. The total amount of the reverse leakage currents IL2 of the memory cells with such bias state flows from the word line WL22 to the word line WL2. Consequently, the word line WL2 typically cannot maintain the low level and the current flowing to the memory cell MC2 of the selected layer changes, so that the sense amp (not illustrated) connected to the bit line BL3 cannot normally detect the current of the memory cell MC2 of the selected layer. Thus, a detection operation may be hindered.